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Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Soroosh Khodami discusses why we aren't ready ...

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by ...

Software has typically been developed with three primary considerations in mind: time to market, budget and functionality. The schedule rules, now more than ever; software has become a competitive ...

One of the questions I often get from customers is “How should I design a board for the best signal integrity?” My expertise is in measurement signal integrity but there is one area where these two ...

The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT). This will take the form of a "test re-use" strategy ...

For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem. But with the arrival of the SoC, it has become clear that testability ...

JTAG has its place but it is not by any means the total solution. Boundary scan, as standardized by IEEE 1149.1 and commonly referred to as JTAG, has truly revolutionized the testability of circuit ...