Business Wire

Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification ...
Business Wire

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...
Design-Reuse

MoSys Partners with Silicom to Provide Stellar Packet Classification IP Optimized for Intel FPGA-Based SmartNICs and Infrastructure Processing Units

Supports 400Gbps Line Rate for 5G Wireless, 5G Packet Core, Broadband Network Gateways, Network Firewalls, Anti-DDoS and Data Center Routing SAN JOSE, CA -- December 13, 2021-- MoSys, Inc.
Design-Reuse

Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications

Significantly expanded portfolio of Cadence design IP optimized for Intel's advanced technologies AI-driven digital and analog/custom EDA solutions certified for Intel 18A technology PDK, delivering ...